The present invention relates generally to integrated circuits, and in particular to testing of integrated circuits.
Delay locked loops (DLL) are often used in integrated circuits (IC) to generate an internal clock signal from an external clock. The internal clock usually has the same frequency with the external clock. Though they have the same frequency, the internal clock is preferable because it is more controllable. The internal clock is also more accurate and matches the operating condition of the IC better than the external clock.
There are different types of DLL. One type of DLL has a delay line for receiving an external clock at one end and producing an internal clock at another end. The delay line is controlled by a controller such as a shift register. The shift register connects to the delay line via a plurality of taps portioned along the delay line. Each of the taps has an equal predetermined amount of delay. The shift register automatically chooses the taps such that once the external clock enters the delay line, the internal clock is generated and has the same frequency with the external clock.
To ensure that the DLL performs properly, the taps of the DLL must be tested. Conventionally, a range of frequency settings is selected to test a corresponding group of taps. The taps at both ends of the group of taps may pass the test, but it is impossible to know if each of the taps in between was used by the DLL during the test. Therefore, there may be a tap that is defected but was not detected by the test.
It is possible to choose a clock frequency in an attempt to test a specific tap. But it is not guaranteed if the specific tap was utilized or tested. The DLL may have used another tap adjacent to the specific tap. This is because each time the DLL operates, the operating condition may change due to changes in variables such as temperature, voltage supply or other process variations within the DLL.
Therefore there is a need for a technique to test a DLL more accurately and more efficiently.
The problems associated with testing DLL and other problems are addressed by the present invention and will be understood by reading the following disclosure. A tap setting override for delay locked loop testability is provided which accurately and efficiently tests delay line taps of a DLL.
In one aspect, an integrated circuit is provided. The integrated circuit includes a delay locked loop (DLL) connected to a test circuit. The DLL includes a plurality of taps connected to a plurality of register cells. The test circuit is capable of enabling any register cell to select a tap to test the DLL.
In another aspect, a method of testing a delay locked loop is provided. The method includes activating a testmode signal. The method also includes activating a bypass signal to cause the shift register to bypass shifting signals from a phase detector. The method further includes decoding a plurality of input signals to produce a tap position signal and enabling the shift register to select a tap based on the tap position signal to test the DLL.